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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
Rev. 02 -- 19 July 2005 Product data sheet
1. General description
The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V for PC1600-PC2700 applications or between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the JEDEC standard for SSTL_2 with Vref normally at 0.5 x VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible, which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTVF16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK going LOW. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and un-driven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the outputs will remain LOW.
Philips Semiconductors
SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
2. Features
s s s s s s s s s s Stub-series terminated logic for 2.5 V VDD (SSTL_2) Designed for PC1600-PC2700 (at 2.5 V) and PC3200 (at 2.6 V) applications Pin and function compatible with JEDEC standard SSTV16859 Supports SSTL_2 signal inputs as per JESD 8-9 Flow-through architecture optimizes printed-circuit board layout ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA Supports efficient low power standby operation Full DDR solution when used with PCKVF857 Available in TSSOP64, LFBGA96 and HVQFN56 packages
3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns Symbol tPHL/tPLH Ci
[1]
Parameter propagation delay, CK/CK to Qn input capacitance
Conditions CL = 30 pF; VDD = 2.5 V VDD = 2.5 V
[1]
Min -
Typ 1.7 2.8
Max -
Unit ns pF
CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VDD2 x fi + (CL x VDD2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VDD = supply voltage in V; (CL x VDD2 x fo) = sum of the outputs.
4. Ordering information
Table 2: Ordering information Tamb = 0 C to +70 C Type number SSTVF16859BS Package Name Description Version HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-1 no leads; 56 terminals; body 8 x 8 x 0.85 mm SOT646-1 SOT536-1
SSTVF16859DGG TSSOP64 plastic thin shrink small outline package; 64 leads; body width 6.1 mm SSTVF16859EC LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm
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Product data sheet
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
5. Functional diagram
SSTVF16859
RESET 1D C1 R Q1A Q1B
CK CK
D1 VREF
to 12 other channels
002aab621
Fig 1. Logic diagram of SSTVF16859
6. Pinning information
6.1 Pinning
55 VDDQ 49 VDDQ 44 VDDQ VDDQ 27 53 Q10A 52 Q11A 51 Q12A 50 Q13A 48 GND 56 Q8A 54 Q9A 45 VDD
47 D13
46 D12
terminal 1 index area Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ 1 2 3 4 5 6 7 8 9
43 D11 42 D10 41 D9 40 D8 39 D7 38 RESET 37 GND 36 CK 35 CK 34 VDDQ 33 VDD 32 VREF 31 D6 30 D5 29 D4 D3 28
002aab618
SSTVF16859BS
Q12B 10 Q11B 11 Q10B 12 Q9B 13 Q8B 14 Q7B 15 Q6B 16 VDDQ 17 Q5B 18 Q4B 19 Q3B 20 Q2B 21 Q1B 22 VDDQ 23 D1 24 D2 25 VDD 26
Transparent top view
Fig 2. Pin configuration for HVQFN56
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
Q13A Q12A Q11A Q10A Q9A VDD GND Q8A Q7A
1 2 3 4 5 6 7 8 9
64 VDD 63 GND 62 D14 61 D12 60 VDD 59 VDD 58 GND 57 D11 56 D10 55 D9 54 GND 53 D8 52 D7 51 RESET 50 GND 49 CK 48 CK 47 VDD 46 VDD 45 VREF 44 D6 43 GND 42 D5 41 D4 40 D3 39 GND 38 VDD 37 VDD 36 D2 35 D1 34 GND 33 VDD
002aab617
Q6A 10 Q5A 11 Q4A 12 Q3A 13 Q2A 14 GND 15 Q1A 16 Q13B 17 VDD 18 Q12B 19 Q11B 20 Q10B 21 Q9B 22 Q8B 23 Q7B 24 Q6B 25 GND 26 VDD 27 Q5B 28 Q4B 29 Q3B 30 Q2B 31 Q1B 32
SSTVF16859DGG
Fig 3. Pin configuration for TSSOP64
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
ball A1 SSTVF16859EC index area 123456 A B C D E F G H J K L M N P R T
002aab619
Transparent top view
Fig 4. Pin configuration for LFBGA96
1 A B C D E F G H J K L M N P R T n.c. Q12A Q10A Q8A Q6A Q4A Q2A Q1A Q12B Q10B Q8B Q6B Q4B Q2B n.c. n.c.
2 n.c. Q13A Q11A Q9A Q7A Q5A Q3A Q13B Q11B Q9B Q7B Q5B Q3B Q1B n.c. n.c.
3 n.c. GND GND VDDQ VDDQ VDDQ GND GND GND VDDQ VDDQ VDDQ GND GND n.c. n.c.
4 n.c. GND GND VDDQ VDDQ VDDQ GND GND VREF VDDQ VDDQ VDDQ GND GND n.c. n.c.
5 n.c. n.c. n.c. D13 D11 D9 D7 n.c. n.c. n.c. D5 D3 D1 n.c. n.c. n.c.
6 n.c. n.c. n.c. D12 D10 D8 RESET CK CK n.c. D6 D4 D2 n.c. n.c. n.c.
002aab620
All VDD and VDDQ are tied internally.
Fig 5. Ball mapping for LFBGA96
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Product data sheet
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Philips Semiconductors
SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
6.2 Pin description
Table 3: Symbol Q1A Q2A Q3A Q4A Q5A Q6A Q7A Q8A Q9A Q10A Q11A Q12A Q13A Q1B Q2B Q3B Q4B Q5B Q6B Q7B Q8B Q9B Q10B Q11B Q12B Q13B VDD VDDQ Pin description Pin TSSOP64 16 14 13 12 11 10 9 8 5 4 3 2 1 32 31 30 29 28 25 24 23 22 21 20 19 17 37, 46, 60 6, 18, 27, 33, 38, 47, 59, 64 HVQFN56 7 6 5 4 3 2 1 56 54 53 52 51 50 22 21 20 19 18 16 15 14 13 12 11 10 8 26, 33, 45 9, 17, 23, 27, 34, 44, 49, 55 LFBGA96 H1 G1 G2 F1 F2 E1 E2 D1 D2 C1 C2 B1 B2 P2 P1 N2 N1 M2 M1 L2 L1 K2 K1 J2 J1 H2 D3, D4, E3, E4, F3, F4, K3, K4, L3, L4, M3, M4, B3, B4, C3, C4, G3, G4, H3, H4, J3, N3, N4, P3, P4 power supply voltage output supply voltage data output data output Description
GND
7, 15, 26, 34, 39, 37, 48 43, 50, 54, 58, 63
ground
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
Table 3: Symbol D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 VREF CK CK RESET n.c.
Pin description ...continued Pin TSSOP64 35 36 40 41 42 44 52 53 55 56 57 61 62 45 48 49 51 HVQFN56 24 25 28 29 30 31 39 40 41 42 43 46 47 32 35 36 38 LFBGA96 N5 N6 M5 M6 L5 L6 G5 F6 F5 E6 E5 D6 D5 J4 J6 H6 G6 A1, A2, A3, A4, A5, A6, B5, B6, C5, C6, H5, J5, K5, K6, P5, P6, R1, R2, R3, R4, R5, R6, T1, T2, T3, T4, T5, T6 input reference voltage positive master clock input negative master clock input Asynchronous reset input. Resets registers and disables data and clock differential input receivers. not connected Data input. Clocked in on the crossing of the rising edge of CK and the falling edge of CK. Description
7. Functional description
Refer to Figure 1 "Logic diagram of SSTVF16859".
7.1 Function table
Table 4: Function selection (each flip-flop) H = HIGH voltage level; L = LOW voltage level; = HIGH-to-LOW transition; = LOW-to-HIGH transition; X = Don't care Inputs RESET H H H L
[1]
Output CK L or H X or floating CK Dn L H X X or floating Qn L H Q0 [1] L

L or H X or floating
Q0 is the previous state of output Qn.
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
8. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI VO IIK IOK IO ICCC Tstg
[1] [2] [3]
Parameter supply voltage input voltage output voltage input clamp current output clamp current continuous output current continuous current through each VDD or GND storage temperature
Conditions
Min -0.5 -0.5 [1] -0.5 [1]
Max +3.6 VDD + 50 50 50 100 +150 0.5 [2] VDD + 0.5 [2]
Unit V V V mA mA mA mA C
VI < 0 V or VI > VDD VO < 0 V or VO > VDD VO = 0 V to VDD
[3]
-65
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 3.6 V maximum. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
9. Recommended operating conditions
Table 6: Symbol VDD Vref VTT VI VIH(AC) VIL(AC) VIH(DC) VIL(DC) VIH VIL VICR VID IOH IOL Tamb
[1]
Recommended operating conditions [1] Parameter supply voltage reference voltage (Vref = VDD/2) termination voltage input voltage AC HIGH-level input voltage AC LOW-level input voltage DC HIGH-level input voltage DC LOW-level input voltage HIGH-level input voltage LOW-level input voltage common-mode input voltage range differential input voltage HIGH-level output current LOW-level output current ambient temperature operating in free air CK, CK CK, CK data inputs data inputs data inputs data inputs RESET PC1600-PC2700 PC3200 Conditions Min VDD 1.15 1.25 Vref - 0.040 0 Vref + 0.310 Vref + 0.150 1.7 0 0.97 360 0 Typ 1.25 1.3 Vref Max 2.7 1.35 1.35 Vref + 0.040 VDD Vref - 0.310 Vref - 0.150 VDD 0.7 1.53 -16 16 +70 Unit V V V V V V V V V V V V mV mA mA C
The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW.
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
10. Static characteristics
Table 7: Static characteristics (PC1600-PC2700) Tamb = 0 C to +70 C; over recommended operating conditions; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol VIK VOH VOL II IDD Parameter input clamping voltage Conditions II = -18 mA; VDD = 2.3 V IOH = -16 mA; VDD = 2.3 V LOW-level output voltage input current (all inputs) supply current IOL = 100 A; VDD = 2.3 V to 2.7 V IOL = 16 mA; VDD = 2.3 V VI = VDD or GND; VDD = 2.7 V IO = 0 mA; VDD = 2.7 V static standby; RESET = GND static operating; RESET = VDD; VI = VIH(AC) or VIL(AC) IDDD dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD; per MHz, clock only VI = VIH(AC) or VIL(AC); CK and CK switching 50 % duty cycle dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK per MHz, per each data input switching 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle Ci input capacitance data inputs; VI = Vref 310 mV; VDD = 2.5 V CK and CK; VICR = 1.25 V; VI(p-p) = 360 mV; VDD = 2.5 V RESET; VI = VDD or GND; VDD = 2.5 V 15 0.01 45 mA mA A Min VDD - 0.2 1.95 Typ Max -1.2 0.2 0.35 5 Unit V V V V V A
HIGH-level output voltage IOH = -100 A; VDD = 2.3 V to 2.7 V
-
9
-
A
2.5 2.5 -
2.8 3.2 2.4
3.5 3.5 3.5
pF pF pF
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
Table 8: Static characteristics (PC3200) At recommended operating conditions; Tamb = 0 C to +70 C; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol VIK VOH VOL II IDD Parameter input clamping voltage Conditions II = -18 mA; VDD = 2.5 V IOH = -16 mA; VDD = 2.5 V LOW-level output voltage input current (all inputs) supply current IOL = 100 A; VDD = 2.5 V to 2.7 V IOL = 16 mA; VDD = 2.5 V VI = VDD or GND; VDD = 2.7 V IO = 0 mA; VDD = 2.7 V static standby; RESET = GND static operating; RESET = VDD; VI = VIH(AC) or VIL(AC) IDDD dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD; per MHz, clock only VI = VIH(AC) or VIL(AC); CK and CK switching 50 % duty cycle dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK per MHz, per each data input switching 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle Ci input capacitance, data inputs input capacitance, CK and CK input capacitance, RESET VI = Vref 310 mV; VDD = 2.6 V VICR = 1.25 V; VI(p-p) = 360 mV; VDD = 2.6 V VI = VDD or GND; VDD = 2.6 V 15 0.01 45 mA mA A Min VDD - 0.2 1.95 Typ Max -1.2 0.2 0.35 5 Unit V V V V V A
HIGH-level output voltage IOH = -100 A; VDD = 2.5 V to 2.7 V
-
9
-
A
2.5 2.5 -
2.8 3.2 2.4
3.5 3.5 3.5
pF pF pF
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
11. Dynamic characteristics
Table 9: Timing requirements (PC1600-PC2700) At recommended operating conditions; VDD = 2.5 V 0.2 V; Tamb = 0 C to +70 C; unless otherwise specified. See Figure 11. Symbol fclock tW tACT tINACT tsu th Parameter clock frequency pulse duration, CK, CK, HIGH or LOW differential inputs active time differential inputs inactive time setup time, fast slew rate setup time, slow slew rate hold time, fast slew rate hold time, slow slew rate
[1] [2] [3] [4] [5] [6] This parameter is not necessarily production tested. Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max), after RESET is taken LOW. For data signal input slew rate 1 V/ns. For data signal input slew rate 0.5 V/ns and < 1 V/ns. CK, CK signals input slew rates are 1 V/ns.
[1] [2] [1] [3]
Conditions
Min 2.5 0.65 0.75 0.75 0.9
Typ -
Max 200 22 22 -
Unit MHz ns ns ns ns ns ns ns
data before CK, CK data before CK, CK data after CK, CK data after CK, CK
[4] [6] [5] [6] [4] [6] [5] [6]
Table 10: Timing requirements (PC3200) At recommended operating conditions; VDD = 2.6 V 0.1 V; Tamb = 0 C to +70 C; unless otherwise specified. See Figure 11. Symbol fclock tW tACT tINACT tsu th Parameter clock frequency pulse duration, CK, CK, HIGH or LOW differential inputs active time differential inputs inactive time setup time, fast slew rate setup time, slow slew rate hold time, fast slew rate hold time, slow slew rate
[1] [2] [3] [4] [5] [6] This parameter is not necessarily production tested. Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max), after RESET is taken LOW. For data signal input slew rate 1 V/ns. For data signal input slew rate 0.5 V/ns and < 1 V/ns. CK, CK signals input slew rates are 1 V/ns.
[1] [2] [1] [3]
Conditions
Min 2.5 0.65 0.75 0.65 0.8
Typ -
Max 210 22 22 -
Unit MHz ns ns ns ns ns ns ns
data before CK, CK data before CK, CK data after CK, CK data after CK, CK
[4] [6] [5] [6] [4] [6] [5] [6]
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
Table 11: Switching characteristics (PC1600-PC2700) At recommended operating conditions; VDD = 2.5 V 0.2 V; Tamb = 0 C to +70 C; Class I; Vref = VTT = VDD x 0.5 and CL = 10 pF; unless otherwise specified. See Figure 11. Symbol fMAX tPD tPDMSS tPHL Parameter maximum input clock frequency propagation delay propagation delay, simultaneous switching HIGH-to-LOW transition time from CK, CK to Qn from CK, CK to Qn from RESET to Qn Conditions Min 200 1.1 1.1 Typ Max 2.5 2.9 5 Unit MHz ns ns ns
Table 12: Switching characteristics (PC3200) At recommended operating conditions; VDD = 2.6 V 0.1 V; Tamb = 0 C to +70 C; Class I; Vref = VTT = VDD x 0.5 and CL = 10 pF; unless otherwise specified. See Figure 11. Symbol fMAX tPD tPDMSS tPHL Parameter maximum input clock frequency propagation delay propagation delay, simultaneous switching HIGH-to-LOW transition time from CK, CK to Qn from CK, CK to Qn from RESET to Qn Conditions Min 210 1.1 1.1 Typ Max 2.2 2.48 5 Unit MHz ns ns ns
11.1 AC waveforms
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; input slew rate = 1 V/ns 20 %; unless otherwise specified. The outputs are measured one at a time with one transition per measurement.
LVCMOS VDD RESET VDD/2 tINACT IDD(1) VDD/2 0V tACT 90 % 10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 6. Inputs active and inactive times
tW VIH input Vref Vref VID VIL
002aab623
VIH = Vref + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = Vref - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
Fig 7. Pulse duration
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
CK VICR CK tPLH tPHL VOH output VTT
002aab624
VICR
Vi(p-p)
VOL
VTT = Vref = VDD/2 tPLH and tPHL are the same as tPD.
Fig 8. Propagation delay times (clock to output)
LVCMOS VIH RESET VDD/2 VIL tPHL VOH output VTT
002aaa376
VOL
VTT = Vref = VDD/2 tPLH and tPHL are the same as tPD. VIH = Vref + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = Vref - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
Fig 9. Propagation delay times (reset to output)
CK VICR CK tsu input Vref th VIH Vref VIL
002aab625
Vi(p-p)
Vref = VDD/2 VIH = Vref + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = Vref - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
Fig 10. Setup and hold times
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
12. Test information
RL = 50
m output under test
CL = 30 pF(1)
test point
002aab622
(1) CL includes probe and jig capacitance.
Fig 11. Load circuit
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
13. Package outline
TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm SOT646-1
D
E
A X
c y HE vMA
Z 64 33
A2 A1 pin 1 index Lp L 1 bp 32 wM detail X
(A 3)
A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.27 0.17 c 0.2 0.1 D (1) 17.1 16.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.1 Z 0.89 0.61 8o o 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT646-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-08-21 03-02-18
Fig 12. Package outline SOT646-1 (TSSOP64)
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
D
B
A
ball A1 index area
A E
A2 A1 detail X
e1
1/2 e
C
v M C A B
e T R P N M L K J H G F E D C B A ball A1 index area
y1 C
y
b
w M C
e
e2
1/2 e
123456 X 0 5 scale 10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.41 0.31 A2 1.2 0.9 b 0.51 0.41 D 5.6 5.4 E 13.6 13.4 e 0.8 e1 4 e2 12 v 0.15 w 0.1 y 0.1 y1 0.2
OUTLINE VERSION SOT536-1
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 00-03-04 03-02-05
Fig 13. Package outline SOT536-1 (LFBGA96)
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm
SOT684-1
D
B
A
terminal 1 index area E
A A1 c
detail X
e1 e 15 L 14
1/2 e
C b 28 29 e vMCAB wMC y1 C y
Eh
1/2 e
e2
1 terminal 1 index area 56 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 8.1 7.9 Dh 4.45 4.15 E(1) 8.1 7.9 Eh 4.45 4.15 e 0.5 43
42 X 2.5 scale e1 6.5 e2 6.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT684-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 14. Package outline SOT684-1 (HVQFN56)
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Product data sheet
Rev. 02 -- 19 July 2005
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Philips Semiconductors
SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
14. Soldering
14.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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Product data sheet
Rev. 02 -- 19 July 2005
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Philips Semiconductors
SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
14.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
14.5 Package related soldering information
Table 13: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Product data sheet
Rev. 02 -- 19 July 2005
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
15. Abbreviations
Table 14: Acronym DDR DIMM ESD HBM PRR SSTL Abbreviations Description Double Data Rate Dual In-line Memory Module Electro Static Discharge Human Body Model Pulse Rate Repetition Stub Series Terminated Logic
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Product data sheet
Rev. 02 -- 19 July 2005
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
16. Revision history
Table 15: Revision history Release date 20050719 Data sheet status Product data sheet Change notice Doc. number 9397 750 15157 Supersedes SSTVF16859_1 Document ID SSTVF16859_2 Modifications:
* *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Table 1 "Quick reference data": - parameter for tPHL/tPLH changed from `propagation delay; CLK to Qn' to `propagation delay; CK/CK to Qn' - Condition column for input capacitance changed from `VCC = 2.5 V' to `VDD = 2.5 V'
*
Section 6 "Pinning information": - Figure 3 "Pin configuration for TSSOP64": pins 6, 18, 27, 33, 38 47, 59 and 64 changed from `VDD' to `VDDQ' - pin description tables consolidated with columns for package-type
* *
Symbol `VREF' changed to `VREF' for pin name, and to `Vref' for reference voltage Figure 2 "Pin configuration for HVQFN56" on page 3: - terminals 26, 33, 45 symbols changed from `VDDI' to `VDD' - terminal 56 symbol changed from `Q8B' to `Q8A'
* *
Table 4 "Function selection (each flip-flop)" on page 7: moved definitions above table; added Table note 1. Table 5 "Limiting values" on page 8: - deleted (old) Table note 1; this information is now placed in Section 18 "Definitions" on page 22. - Added symbol `ICCC' to parameter `continuous current through each VDD or GND'
* *
Section 9 "Recommended operating conditions" on page 8: under Min and Max columns, values previously expressed with unit `mV' re-written as equivalent `V' value. Table 7 "Static characteristics (PC1600-PC2700)" on page 9: - IDD(max) for `static operating' condition changed from `25 mA' to `45 mA' - IDDD(typ) for `clock only' changed from `20 A' to `15 A' - parameter for IDDD modified: added `per MHz' to parameter, changed Unit to `A'
* *
SSTVF16859_1
Table 8 "Static characteristics (PC3200)" on page 10: parameter for IDDD modified: added `per MHz' to parameter, changed Unit to `A' Added Section 14 "Soldering", Section 15 "Abbreviations", and Section 20 "Trademarks". Product data sheet 9397 750 13077 -
20040712
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Product data sheet
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SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
17. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
20. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
19. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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Product data sheet
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Philips Semiconductors
SSTVF16859
13-bit 1 : 2 SSTL_2 registered buffer for DDR
22. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 19 Package related soldering information . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information . . . . . . . . . . . . . . . . . . . . 22
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 19 July 2005 Document number: 9397 750 15157
Published in The Netherlands

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